Computer chip manufacturing processes typically include the formation of p-n junctions in a semiconductor substrate which are connected by polysilicon which is deposited, masked, and etched to form a patterned polysilicon surface. The patterned polysilicon surface connects with the p-n junctions so as to form numerous semiconductor devices on the semiconductor substrate. Typically, one or more layers of dielectric is then deposited over the surface of the semiconductor. The dielectric is then masked and etched to expose portions of the polysilicon surface or "gate", as well as diffusion areas (sources and drains) through openings which are commonly referred to as contacts. Tungsten is used to fill the contact hole which is then commonly referred to as a plug. A layer of metal or "first metal" is then deposited over the surface of the semiconductor. Typically aluminum is sandwiched in between layers of titanium, titanium/tungsten alloy or titanium nitride. The metal sandwich overlies the layer of dielectric and electrically contacts the plugs so as to allow for contact between the first metal layer and the semiconductor devices. The first metal layer is then masked and etched so as to form metal lines or routing "interconnects" which connect to the various semiconductor devices through the vertical contacts. Alternate layers of dielectric and metal are then formed over the first metal layer, where subsequent vertical through-hole interconnects are referred to as "vias".
As the complexity of computing devices and data storage devices has increased, there has been a need to place more semiconductor devices on each computer chip. This need has led to smaller and smaller devices and interconnects. However, as devices and interconnects have become smaller and smaller the process limitations of depositing and etching metal so as to form interconnects has imposed limitations on further size reductions in processing technology. This is primarily due to the limitations imposed by the patterning (lithography and etch) process. These limitations make increasingly smaller interconnects difficult if not impossible to etch since the interconnects are extremely small, and since they must be spaced closely together. The inability to control the metal etch process with the needed degree of accuracy leads to non uniform interconnect width or to shorts between adjacent metal lines. The non-uniform interconnect width leads to electrical cross-talk between interconnects and non uniform resistance between interconnects of equal length. As processing devices get smaller and smaller, the inaccuracies in the depth and width of the metal layer interfere to an increasing degree with signal processing. Variable line resistance can result in signal delay which creates timing problems. In addition, incomplete etch in tightly pitched metal etch processes causes yield loss and drives up manufacturing costs.
One recent process for obtaining the small metal lines and contacts needed for the 0.18 micrometer process generation and for subsequent smaller processing generations is the use of damascene processing techniques. In damascene processing techniques, devices and gates are created as described above. The dielectric layer which is typically an oxide, commonly referred to as an Inter Metal Oxide (IMO) is deposited over the semiconductor surface. The oxide layer is polished so as to obtain a planar upper surface. Prior art FIG. 1A shows semiconductor substrate 115 after oxide layer 108 has been deposited over gates 106-107 and over semiconductor substrate 115 and after polishing of oxide layer 108 so as to obtain a planar upper surface.
Oxide layer 108 is then masked and etched to form openings or vias for contact between the semiconductor devices and a first metal layer. Prior art FIG. 1B shows semiconductor device 100 after mask and etch steps have formed via 109. Via 109 exposes a portion of gate 107.
A second mask and etch process is then performed to form trenches in the top of the oxide layer. Prior art FIG. 1C shows the structure of prior art FIG. 1B after mask and etch steps have formed trench 111 and trench 112 within oxide layer 108. Trench 112 partially overlies via 109.
A metal layer is then deposited over the semiconductor surface such that it fills the vias and the trenches. As shown in prior art FIG. 1D, metal layer 120 fills via 109 and trenches 111-112 and it overlies the top surface of oxide layer 108.
The metal which overlies the top surface of the IMO is removed by a chemical mechanical polishing (CMP) step. As shown in prior art FIG. 1E, the polishing step removes that portion of metal layer 120 which overlies the top of oxide layer 108 so as to form a planar surface and so as to form interconnect 125 and interconnect 126 and contact 127. Contact 127 electrically connects interconnect 126 to gate 107. This process leaves a planar surface and allows for the formation of small, closely spaced interconnects and contacts.
The success of damascene processes is primarily due to the fact that it is generally easier to etch oxides than it is to etch metal since there is more margin for error (oxide under etching changes the resistance but does not cause a short). Moreover, by using oxide etch processes, thinner structures and closer spacing between structures are possible than are possible using metal etch techniques. Another advantage of damascene processes is the ability to use copper as a material for interconnects and contacts. Since copper is hard to etch, it is seldom used in current wafer processing systems. However, copper may be deposited such that it fills the trenches and vias and it may be polished so as to obtain a damascene structure with copper interconnects and contacts.
The depth of the trenches is controlled by the use of timed etches. Though the use of timed etches is currently the best method for obtaining the required depth for the trenches, the timed etch processes produces trenches with non uniform depths. The depths of individual trenches vary when using timed etch techniques due to pattern density effects, RIE lag (reduced etch rates for smaller openings), center to edge non uniformity, and wafer to wafer non uniformity. Since the depths of the trenches of the damascene process varies due to the timed etch process, the interconnects formed have non-uniform thicknesses. The non-uniform thicknesses between interconnects causes non-uniform resistivity between interconnects which leads to timing problems and signal interference. Moreover, the non-uniform thickness between interconnects decreases yield and throughput.
Recent prior art processes have used a stop layer of silicon nitride as an etch stop. In these processes a first oxide layer is deposited over a semiconductor substrate such that it overlies gate, source and drain structures. The first oxide layer is planarized and a layer of silicon nitride layer is deposited over the first oxide layer. A second oxide layer is then deposited over the silicon nitride layer. A conventional oxide etch is used to etch through the second oxide layer to expose the silicon nitride layer. However, since a different etch chamber and/or etch chemistry is required to etch through silicon nitride, the plasma feed gas is changed to a different chemistry before etching the silicon nitride layer. An etch chemistry of, for example, one part hydroflorocarbon to ten parts O.sub.2 may be used to etch through the silicon nitride layer.
After etching through the silicon nitride layer where desired (e.g. above gate or sources or drains), the wafer is stripped of photoresist and remasked in a pattern indicating trench locations. The wafer is then etched again using an oxide etch chemistry to remove portions of the first oxide layer so as to form a via extending to the gate or source or drain to be contacted. Simultaneously, the second oxide layer is being etched so as to form trenches. Since a standard oxide etch will not etch through the silicon nitride layer, portions of the silicon nitride layer will form the bottom surface of trenches. Therefore, the bottom surfaces of the trenches will be uniform and planar. The presence of the remaining nitride serves as a hard mask for the completion of the concurrent via etch. Next, a metal layer is deposited and polished to complete the damascene formed structure.
Though the use of silicon nitride as an etch stop allows for the formation of interconnects having relatively planar bottom surfaces, expensive additional process steps are required. In particular, the wafer must be placed in a separate high vacuum plasma CVD reactor for nitride deposition. In addition, since the chemistry needed to etch silicon nitride is oxygen rich (different from the chemistry of oxide etch processes), the etchant must be changed between steps. This also adds processing time and resist is consumed, which degrades the etch profile as the etch proceeds.
Thus, a need exists for a damascene-formed structure which includes interconnects having uniform thicknesses. A further need exists for a method for forming a damascene structure which minimizes fab process time and which allows for the less expensive manufacture of damascene structures. Moreover, a damascene structure and a method for forming a damascene structure is needed that will increase yield and throughput of manufacturing. The present invention meets the above needs.